1. Technical Field
The present disclosure relates to a device with contact connections that comprises at least one component integrated in a substrate material.
2. Description of Related Art
There are known processes in which components or integrated circuits on a semiconductor chip or still joined to a semiconductor wafer are provided with a housing and electrical terminal contacts. If the mounting of the chip or of the integrated circuit and the connection of the contact regions of the chip to the contacts of the housing which lead to the outside takes place while the arrangement is still joined to the wafer, a mounting process of this type is generally known as a “wafer level package process”.
A number of such processes are to be found in the prior art. These processes are generally based on it being possible for the connections to the contact regions on the chips or in the integrated circuits to be produced directly, as is the case without problems, for example, in the case of memory chips.
However, this takes no account of the fact that the optically active surface has to be left clear in the mounted state, for example on a printed circuit board, as is the case, for example, in chips with an integrated sensor or optical component.
To this extent, WO 99/40624 has disclosed a process in which it is attempted to ‘overcome the problem outlined above by leading the terminal contacts which lie at the active component from the active side to the opposite underside of the wafer or of the chip. Further contact can then be made with the terminal contacts which have been led downward in a known way. Moreover, a similar process is described in “Wafer Level Chip Scale Packaging: Benefits for Integrated Passive Devices”, Clearfield, H. M.; Young, J. L.; Wijeyesekera, S. D.; Logan, E. A.; IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, pp. 247-251.
The above-mentioned process is distinguished by the fact that, after a glass covering has been applied to the optically active front surface of a wafer, trenches are produced along the * underside of the wafer, dividing the wafer into individual chip regions. As part of the production of the trenches, the terminal contact locations which are located on the active side of the wafer, in each case at the transition region between two chips, are split and thereby uncovered in the trenches. After the trenches have been produced, to completely house the wafer or the chips, a pane of glass is adhesively bonded over the trenches and is cut into in an appropriate way, such that the trenches in the wafer and the terminal contact locations are once again freely accessible. Then, contact tracks are deposited in the trenches which have been produced, as a result of which it is supposed to be possible to make contact with the terminal contact locations and to lay the contact location on the back surface of the housed chip.
Although the proposed process leads to through-contact being made with the terminal contacts from the active front surface of the chip or wafer to the passive back surface, a number of significant drawbacks arise in the process, so that chips which have been produced using the claimed process are disproportionately expensive. This results, inter alia, from the fact that the trenches which are to be produced in the known process are significantly wider than would normally be encountered during standard division or dicing of a wafer. As a result, this means that the distances between the chips or the integrated circuits have to be relatively great, so that there is space for fewer chips on a wafer. If only for this reason, the known process provides only a relatively low chip yield from a semiconductor wafer. Furthermore, the production process as proposed is also relatively slow. On the one hand, this is in particular because the trenches have to be ground in sequentially, and secondly this is because during production of the trenches, what is known as the dicing saw can only operate at a relatively slow advance rate. Apart from all this, the dicing saws which have to be used are very expensive. A further significant problem of the process described in WO 99/40624 is that the terminal contacts are uncovered by dividing them when the trenches are being ground open. Dividing the terminal contacts in this way requires a very high level of dimensional accuracy, since otherwise at least part of the contact may be destroyed. However, even if accurate cutting of the terminal contact is achieved, it is not easy to produce a contact connection with the terminal contacts which have been uncovered in this way. The reasons for this are in particular that in accordance with the prior art contact is to be made by depositing contact tracks on the walls of the trenches, which are inclined in the wafer, but uniform and therefore targeted deposition is only possible perpendicular to the deposition direction. Further processes for making through-contact with chips are also described in “Future Systems-on-Silicon LSI Chips”, Koyanagi, M; Kurino, H; Lee, K. W.; Sakuma, K, IEEE Micro, July-August 1998, pp. 17-22, WO98/52225 and DE 197 46 641. However, these processes are unsuitable for the packaging of optical chips.